1. Field of the Invention
This invention relates to a method for selectively depositing metal (usually copper) in structures for silicon wafer semiconductor structures.
2. Description of the Prior Art
The double damascene process has allowed copper to be used for the wires on semiconductor wafers instead of aluminum. Copper cannot be efficiently plasma etched as aluminum was. The wafer is etched with grooves in the oxide coating for the wires that will connect devices once the process is complete. Holes are etched in the bottom of the grooves to make contact with the devices in the layer of the wafer below. The wafer is coated with copper so that the copper fills the grooves and holes. The copper coating is polished back to reveal the damascene wires that make contact with the layers below because the copper is filling the holes that go down to that layer.
U.S. Pat. No. 6,261,954 B1 by Paul Ho et. al., which teaches a METHOD TO DEPOSIT A COPPER LAYER focuses on depositing a good layer of copper for the double damascene process. The use of polar organic solvents in the aqueous copper solution to deposit a good layer is discussed in this patent. The wasteful coating of the whole wafer with copper is explained so that a majority of the copper that is deposited will have to be polished off to reveal the double damascene structure.
U.S. Pat. No. 6,716,743 B2 by Naoki Nagashima which teaches a METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE employs a second barrier layer over the copper to allow the double damascene pattern to be made with no cupping of the top of the copper surface. The method employs a covering layer of the barrier material usually titanium nitride or tantalum nitride to allow the surface of the copper to be polished without cupping. Still much copper is wasted in the process because the whole surface of the wafer is coated with copper and then it is polished back to reveal the double damascene structure.
U.S. Pat. No. 6,815,336 by Shau-Lin Shue and Syun-Ming Jang which teaches PLANARIZATION OF COPPER DAMASCENE USING REVERSE CURRENT ELECTROPLATING AND CHEMICAL MECHANICAL POLISHING uses a photo resist mask that exposes unneeded copper that is removed by reverse current electroplating. Still, much copper is wasted because the whole wafer must be coated with copper before this process can reduce the amount of copper polished off.
At present in double damascene patterning of a wafer the oxide is patterned with photo resist and the via holes or contact holes are etched to the layer below. Then the photo resist is removed and the oxide is patterned with photo resist and the channels that will be where the wires will be for the metal layer are etched. Then the photo resist is removed and the metal is put all over the wafer first the barrier layer and then the copper. Then the wafer is polished back to reveal the metal lines imbedded in the oxide layer using chemical mechanical polishing (CMP) processes. This requires that most of the metal put on the wafer be polished off. Only the metal in the via holes, contact holes, and metal lines is left on the wafer. What a waste. If the metal could be grown only in the places that it is needed, this would save several steps of the process.